Presently, many electronic systems use the function of clock generation and multiplication. Examples include, yet are not limited to, a graphics digitizer for flat panel displays and LCD computer monitors, and the analog read channel integrated circuit of a hard disk drive. Clock generators, typically known as frequency synthesizers, also find use in wireless applications where they are used to generate local oscillators in transmitters and receivers with fine channel spacing and often times modulation applied to the carrier signal. Frequency synthesizers are also commonly used to generate a clock to establish the time to sample a data signal.
Traditionally, frequency synthesizers are classified into two distinct categories: fractional-N synthesizers which generate an output clock that is a non-integer multiple of the input clock and integer-N synthesizers which generate an output clock that is an integer multiple of the input clock. Fractional-N synthesis offers an advantage over integer-N based synthesis since it allows a finer frequency resolution than the reference or input frequency, as described, for example, in U.S. Pat. No. 3,928,813, Issue Date: Dec. 23, 1975, “Device for synthesizing frequencies which are rational multiples of a fundamental frequency”. However, there is a tradeoff for the improvement in the frequency resolution. Prior art fractional-N synthesizers have an inherent performance limitation due to the use of a fractional (i.e. non-integer) multiplication factor between the output clock and input clock. This performance limitation exists in addition to all other error terms found in classical integer-N clock generators/multipliers. In particular, the actual clock edges show a deviation from the timing of an ideal periodic clock signal, a phenomenon commonly referred to as clock jitter. Jitter reduces the timing precision and, hence, signal quality. Moreover, since the output clock of a frequency synthesizer is often sent to many components in a system, any jitter present in the frequency synthesizer's output clock can propagate throughout the multiple components resulting in a degradation of performance, and possibly even failure, across larger systems.
The reduced system performance that can result from the use of fractional-N synthesizers can limit the usability of such synthesizers. For example, according to digital communication standards, such as Serial ATA as described in High Speed Serialized AT Attachment, Serial ATA Working Group, Revision 1.0a, Jan. 7, 2003, PCI Express as described by PHY Interface for the PCI Express Architecture, Intel Corporation, Version 0.95, Apr. 25, 2003, and Fiber Channel as described by Fiber Channel Physical Interfaces: FC-P1-2, American National Standard for Information Technology, Revision 4.0, July, 2003. An incoming data stream is sampled into a sequence of ones and zeros to extract the information contained in the incoming data. To achieve optimum performance, the clock used to sample the input data is positioned in the center of the data bit. The system performance of such systems is typically measured in terms of bit error rate (“BER”) where BER is the probability of having a bit error. If the jitter present on the sampling clock is greater than half a data-bit period in either direction from the optimal sampling time, then a bit error can occur. Since the additional jitter introduced by a fractional synthesizer can significantly degrade BER, fractional synthesizers are traditionally not used in data sampling applications.
Data sampling is not the only area of application where usability of fractional synthesizers is limited due to jitter. Similar limitations of use exist in other areas. For example, increased jitter associated with fractional frequency synthesizers can limit the maximum resolution at which a clear picture can be viewed on a flat panel display or LCD computer monitor. Increased jitter can also reduce the signal-to-noise ratio for a hard disk drive read path limiting maximum data density and speed.
As a result of usability limitations, numerous attempts have been made at constructing reduced jitter fractional synthesizers. Before discussing these attempts, it is useful to review the basics of frequency synthesizers. Typically, a frequency synthesizer can be implemented using a charge pump phase locked loop (PLL). The general structure of a prior art PLL consists of a phase and frequency detector (PFD), a charge pump (CP), a proportional and integral path loop filter (LF), a voltage-controlled oscillator (VCO), and a divider in the feedback path as described in ‘Phase Locked Loops’ by R. E. Best, McGraw-Hill, 1993. PLLs often contain additional dividers in the reference path before the PFD and after the VCO outside of the feedback loop to allow greater control over output clock frequency.
The PFD generates an output signal that is proportional to both the frequency and phase difference between its two inputs: the reference input and the output of the feedback divider. The charge pump and loop filter transform this signal into a voltage waveform while providing low-pass filtering. The poles and zeroes of the loop filter as well as the charge pump current and VCO gain determine the characteristics and phase transfer function of the PLL. The output voltage of the loop filter controls the frequency of the VCO. The VCO generates the output clock of interest that is sent to the feedback divider as well as out of the PLL; optionally through a post-divider in the output path.
The feedback divider divides the VCO clock down to the frequency of the reference clock. Since the PLL is a negative feedback system in a closed-loop configuration, the PLL will eventually settle to the operating point where the reference clock and output clock of the feedback divider are phase and frequency locked. In this condition, the frequency ratio between the output clock and the reference clock is determined solely by the division factor in the feedback path between the VCO and the PFD. An integer divider provides an integer-N frequency synthesizer, whereas a fractional divider will provide a Fractional-N frequency synthesizer.
There are two popular methods to accomplish a fractional divider in the feedback path. The first method uses a dual-modulus divider to switch between two integer divide values as described in U.S. Pat. No. 3,928,813, Issue Date: Dec. 23, 1975, “Device for synthesizing frequencies which are rational multiples of a fundamental frequency”, and U.S. Pat. No. 3,976,945, Issue Date: Aug. 24, 1976, “Frequency synthesizer”. The fractional division value is then determined by the average divide value, that lies somewhere between the two integer divide values and is determined by the duty-cycle of the dual-modulus divider. A disadvantage of this method is that it can produce unwanted spectral components at the VCO output called fractional spurs. These fractional spurs lead to increased jitter at the output clock of the PLL. The frequency offset of the fractional spur is determined by the duty cycle of the dual modulus divider and can occur at relatively low frequencies relative to the PLL loop bandwidth. Since the PLL acts like a low-pass filter with respect to jitter sources at the inputs to the PFD, low-frequency fractional spurs that fall below the PLL loop bandwidth will contribute directly to output clock jitter.
The second method uses a multi-phase fractional divider in the feedback path of the PLL as described in J. Craninckx, M. Steyaert, IEEE Journal of Solid State Circuits, “A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7 um CMOS”, July, 1996, and U.S. Pat. No. 5,970,110, Issue Date: Oct. 19, 1999, “Precise, Low-Jitter Fractional Divider using Counter of Rotating Clock Phases”. This method uses multiple phases at either the VCO frequency or a divided down VCO frequency to equally span one full clock period. The fractional divider then performs phase interpolation or phase selection between these multiple phases to accomplish fractional divide values. This method allows finer frequency resolution and smaller phase quantization error than a dual-modulus divider. The use of multiple phases is often not a problem since it also allows for multiple output clock phases that are often used in a given application. The method, however, still suffers from fractional spurs at a frequency offset determined by the desired fractional division value. This method also suffers from the additional error term introduced by phase mismatch between the multiple phases of the VCO or delay paths within the VCO buffers or multi-phase divider. Such dividers are also not able to divide by an arbitrary fraction M. N where M is the integer part and N is the fractional part of a real number.
An improvement to fractional synthesizers can be attained by adding a delta-sigma modulator (“DSM”) to control the feedback fractional divider. This was originally reported in B. Miller, B. Conley, IEEE 44th Annual Symposium on Frequency Control, “A Multiple Modulator Fractional Divider”, May, 1990, T. Riley, M. Copeland, Source: IEEE Journal of Solid State Circuits, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis”, May, 1993, and U.S. Pat. No. 4,965,531, Issue Date: Oct. 23, 1990, “Frequency synthesizers having dividing ratio controlled by sigma-delta modulator”. A delta-sigma modulator produces a quantized (one to several bits) output from a high resolution input with the error resulting from this quantization spectrally shaped to reduce its spectral density at frequencies approaching direct current or zero frequency (“DC”) and multiples of the DSM clock frequency. This randomization and spectral noise shaping applies to the quantization noise inherent in fractional dividers, thereby reducing the quantization noise level within the passband of the PLL. This allows a significant portion of the quantization noise to be removed by the loop filter of the PLL, leading to an improved output clock jitter. Another advantage of using a delta-sigma fractional synthesizer is that the synthesizer resolution (i.e., frequency step size) can be made arbitrarily small by adding more bits to the delta-sigma modulator.
A disadvantage of fractional synthesizers based on DSMs is that the time quantization step size of the delta-sigma modulator is one reference clock VCO period. That is, because the DSM is used to control a dual modulus N/N+1 type fractional divider, the divider can only change by integer amounts. This limits the step size for the DSM to one reference cycle. Also, the clock rate of the DSM is limited to the reference clock rate since this is the update rate of the dual modulus divider. Therefore, the quantization noise spectrum is whitened up to half the frequency of the reference input, with a large proportion of its energy still falling within the passband of the PLL.
High-order DSMs have been utilized to remove the quantization error introduced by fractional synthesizers based on DSMs. However, since the power dissipation and chip area used for a DSM scales directly with its respective order, use of this technique requires a tradeoff between the amount of fractional quantization error suppression and increased overall power consumption and size. An additional disadvantage of a high order DSM is that the PLL loop filter is typically of the same or greater order than the DSM to adequately suppress the out-of-band quantization noise. Designing PLLs with loop filters greater than second order becomes extremely difficult due to stability limitations in this negative feedback system. Because of these limitations, fractional synthesizers employing delta-sigma modulators typically use only second or third order delta-sigma modulators, limiting the practical improvement of using delta-sigma modulation to reduce the fractional quantization noise and hence jitter.
The earliest attempt to combine the use of a multi-phase feedback divider and delta-sigma modulation was previous research of Dr. Ken Martin, inventor of the present invention, and one of his Master's students and was reported in Wynstan Ka-Wai Tong supervised by Ken Martin, Master's Thesis at the University of Toronto, “A GHz CMOS Frequency Synthesizer for Mobile Communications”, Master's Thesis at the University of Toronto, July 1997. In the reported work (and as is found in other prior art) the delta sigma modulator is clocked at the reference clock rate of the PLL. Tong, thus, does not solve the problem of constructing a jitter reduced frequency synthesizer combining a multi-phase feedback divider with high speed delta-sigma modulation.
An alternative method of implementing a multi-phase fractional divider is reported in C. H. Park, O. Kim, B. Kim, IEEE Journal of Solid State Circuits, “A 1.8 GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching”, April, 2003. This approach allows operation of the fractional divider at higher clock frequencies since the feedback divider consists of a single phase integer divider that is followed by a phase select multiplexer to realize the fractional division control. The output of the integer divider at the reference clock frequency (fref) is sampled with the higher-speed VCO to get the phase resolution of the VCO at the update rate of the reference input and sent into a phase select multiplexer. This allows simpler implementation of the phase select multiplexer since it only operates at the reference clock rate and therefore allows for operation at higher VCO rates. An accumulator is used to control the feedback division ratio with the input to the modulo-Np (where Np=number of phases used) accumulator representing the fractional divider value and the carry out of the accumulator used to add or subtract one VCO cycle from the integer divider. This type of fractional feedback divider has the purported advantage that ideally it introduces no fractional quantization error, although its frequency resolution is limited to the reference frequency divided by the number of phases used (i.e., fref/Np). It was also found that this class of fractional divider is very susceptible to phase mismatch errors leading to fractional spurs and a corresponding degradation in output clock jitter performance. A further limitation of this class of fractional divider is that the update rate is limited to the reference clock frequency of the PLL since this is the clock rate at the output of the integer divider.
A recent improvement to this type of fractional divider is to add delta-sigma modulation to whiten and spectrally shape the delay error produced by the phase mismatch as described in T. Riley, J. Kostamovaara, IEEE Transactions on Circuits and Systems II, “A Hybrid Delta-Sigma Fractional-N Frequency Synthesizer”, April, 2003. The delta-sigma modulator randomizes and spectrally shapes the delay error introduced by the phase mismatch, resulting in an improvement in output clock jitter. Since multiple phases are used with delta-sigma modulation this reduces the quantization step size by an amount equal to the number of phases.
Although the fractional divider in this case is a multi-phase fractional divider, the update rate of the phase select multiplexer is at the reference rate limiting the maximum clock frequency of the delta-sigma modulator to the reference clock frequency. Another disadvantage of this approach is that a high-order modulator is used to reduce the phase mismatch error to negligible levels. In the reported work, for example, a seventh order modulator is used. This high an order of delta-sigma modulator introduces significant complexity that increases power and area consumption in implementation. Moreover, a high-order delta-sigma modulator also uses either a higher-order loop filter in the PLL or a lower PLL loop bandwidth to suppress the larger peak quantization noise inherent in using a high-order modulator. Thus, a fractional synthesizer with a delta-sigma modulator of order greater than three is generally not used and this limits the practical usefulness of this approach.
Another alternative to reducing phase quantization noise in a frequency synthesizer can be implemented using a dual-modulus fractional divider followed by compensation within the loop filter of the PLL to cancel the quantization noise (S. E. Meninger, M. H. Perrot, IEEE Transactions on Circuits and Systems II, “A Fractional-N Frequency Synthesizer Architecture Utilizing a Mismatch Compensated PFD/DAC Structure for Reduced Quantization-Induced Phase Noise”, November, 2003). This method has been used with an accumulator, as opposed to a delta-sigma modulator, to control the fractional divider because in this case the quantization error is more predictable. The accumulator output is also sent to a digital-to-analog converter (DAC) to cancel the fractional quantization noise in the loop filter of the PLL. This approach is limited by analog matching precision that results in incomplete phase-error signal cancellation and spurious feed-though.
Another source of jitter in multi-phase or phase switching fractional dividers are glitches which can also cause the frequency synthesizer to fall out of phase lock (see J. Craninckx, M. Steyaert, IEEE Journal of Solid State Circuits, “A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7 um CMOS”, July, 1996 (“Craninckx and Staeyart”), N. Krishnapura and P. Kinget IEEE Journal of Solid State Circuits, “A 5.3-GHz programmable divider for HiperLAN in 0.25 um CMOS”, July 2000 (“Krishnapura”), M. Perrot Ph.D. dissertation “Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers” Massachusetts Institute of Technology, September 1997 (“Perrot”), A. Benachour, S. Embadi, and A. Ali proceedings of the IEEE Custom Integrated Circuits Conference “A 1.5 GHz sub-2 mW CMOS dual modulus prescaler” May 1999 (“Benachour”), and Keliu Shu Pd.D. dissertation “Design of a 2.4 GHz CMOS monolithic fractional-N frequency synthesizer” Texas A&M University, May 2003 (“Shu”)).
Attempts have been made to eliminate such glitches. However, these attempts have their disadvantages and do not allow robust operation of a phase switching fractional divider at high clock rates without imposing limitations. For example, the system as disclosed by Krishnapura is sensitive to process variation and thus not suitable for large scale production. In Perrot, feedback from the phase select multiplexer is used. However, Perrot's approach reduces the maximum operating speed. A synchronizing flip-flop is used in Benachour to retime the phase select multiplexer control signal. In addition to the technique described above, Krishnapura also uses a retiming circuit in a attempt to reduce glitches. However, using such synchronization or retiming does not render the phase-switching operation any more robust because it can be difficult to implement in a high-speed circuit and the timing requirements of this circuit are very stringent. Moreover, Krishnapura's multi-faceted approach introduces more complexity that increases power consumption and size in implementation.
According to the disclosure in Shu, phase switching occurs in only one direction. By designing a phase rotator to only pick a previous phase, a glitch can be avoided since a glitch can only occur when the phase rotator rotates to the next phase, provided that all other timing requirements are met. Thus, Shu does not remove glitches but attempts to avoid a condition under which a glitch can occur. Specifically, Shu's disclosure does not contain an explicit circuit to remove glitches. Moreover, since Shu's disclosure restricts phase shifts to only one direction, the fractional tuning range is cut in half.